1. Field of the Invention
The present invention generally relates to integrated circuit protection devices and, in particular, to a device for protecting an integrated circuit from damage which can be caused by an electrostatic discharge into an output terminal.
2. Description of the Related Art
One chronic problem associated with semiconductor integrated circuits is the damage which can be caused to the circuitry by an electrostatic discharge (ESD) into any one of the external connector pins. In handling a semiconductor chip, a simple static electricity discharge from a finger tip can achieve an instantaneous level of thousands of volts. It is commonly known that a much smaller static voltage discharge into the die interior can result in destruction due to junction breakdown, contact breakdown, thermal burnout and, in circuits using gated components, breakdown of the gate oxide layers.
ESD protection has become a topic of increasing interest as the device dimensions within a chip decrease and, therefore, make the products more susceptible to the harmful effects of an ESD event.
In general, ESD protection devices can be separated into two categories: input and output protection designs. Because of different operational requirements, different schemes are needed for each. Normally, a chip output cannot tolerate a high resistance factor. This becomes even more serious if the voltage range of the output increases.
The typical ESD protection scheme relies on either output junction breakdown or gated diode breakdown of the output transistors. FIG. 1 shows an example of a typical arrangement used for ESD protection of an integrated circuit. The layer of the output buffer transistors may be optimized to afford some protection. If the output transistors N1, N2 are laid out with a proper spacing between the contacts and gates, then the failure mechanism is dominated by output junction breakdowns [designated by the encircled areas in FIG. 1(b)]. The ESD voltage of this failure mode is slightly higher than that for a gated diode breakdown arrangement. An example of such a device is shown in U.S. Pat. No. 4,139,935 to Bertin et al. In comparison to this example, the present disclosure teaches an invention which is independent from the buffer stage.
In general, the state-of-the-art ESD protection devices achieve the ability to dissipate approximately 2000 volts into a connection pin. However, destructive junction breakdown has been found to occur in shallow junction CMOS circuits at much lower ESD voltages. Hence, there is a need for devices which will provide greater ESD protection for integrated circuits.